/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2018-2019. All rights reserved.
 * Description: Hi309x uboot header file for platform definations
 * Author: l00416998
 * Create: 2018-05-10
 */
#ifndef __HI309X_MEMMAP_H__
#define __HI309X_MEMMAP_H__

#define MMU_DRIVER_ADDR 0x08600000ULL
#define MMU_GIC_ADDR 0x24000000ULL
#define MMU_LOCALBUS_MEM_ADDR 0x30000000ULL
#define MMU_LOCALBUS_MEM_SIZE 0x2FFFFFFF

#define DDR_BASE_ADDR (0x80000000)
#define IBMC_SYS_RSV_SIZE (0x7200000) /* The first 114 MB of DDR is reserved for dedicated use. */
#define CONFIG_SYS_SDRAM_BASE (DDR_BASE_ADDR + IBMC_SYS_RSV_SIZE)
#define CONFIG_SYS_SDRAM_SIZE (0x20000000) /* 512M */

#define CPU_RELEASE_ADDR_LEN (0x60)
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000 - CPU_RELEASE_ADDR_LEN) /* 0x8727ffa0 */
#define CPU_RELEASE_GDTBL (CPU_RELEASE_ADDR + 0x8) /* 0x8727ffa8 */
#define CPU_RELEASE_VBAR (CPU_RELEASE_ADDR + 0x10) /* 0x8727ffb0 */
#define CPU_RELEASE_MMU_PAGE (CPU_RELEASE_ADDR + 0x18) /* 0x8727ffb8 */
#define CPU_RELEASE_MMU_TCR (CPU_RELEASE_ADDR + 0x20) /* 0x8727ffc0 */
#define CPU_RELEASE_BOOT_SYNC (CPU_RELEASE_ADDR + 0x28) /* 0x8727ffc8 */

#define GMAC_MDIO_SYNC (CPU_RELEASE_ADDR + 0x2c)
#define GMAC_LOCK_SYNC (CPU_RELEASE_ADDR + 0x30)

#define HI_UBOOT_BASE_ADDR (DDR_BASE_ADDR + IBMC_SYS_RSV_SIZE) // 0x87200000
#define HI_UBOOT_MEM_SIZE 0x8000000 // 128M

#define HI_CORE0_BASE_ADDR (HI_UBOOT_BASE_ADDR + HI_UBOOT_MEM_SIZE) // 0x8f200000
#define HI_CORE0_MEM_SIZE 0x4280000
#define HI_CORE0_STACK_SIZE 0x800000 // 8M
#define HI_CORE0_STACK_BASE (HI_CORE1_BASE_ADDR - 16)

#define HI_CORE1_BASE_ADDR (HI_CORE0_BASE_ADDR + HI_CORE0_MEM_SIZE) // 0x93480000
#define HI_CORE1_MEM_SIZE 0x4280000
#define HI_CORE1_STACK_SIZE 0x800000 // 8M
#define HI_CORE1_STACK_BASE (HI_CORE2_BASE_ADDR - 16)

#define HI309X_TRIGGER_MAP 0xf
#define MMU_DDR_ADDR 0x80000000ULL
#define MMU_DDR_SIZE 0x7FFFFFFFULL
#define MMU_PAGE_BEGIN 0x8a000000
#define MMU_PAGE_END (MMU_PAGE_BEGIN + 0x8000)

#define MMU_OPENAMP_ADDR 0 /* invalid */
#define MMU_OPENAMP_ADDR_SIZE 0 /* invalid */

#define HI_CORE2_BASE_ADDR (HI_CORE1_BASE_ADDR + HI_CORE1_MEM_SIZE) // 0x97700000
#define HI_CORE2_MEM_SIZE 0x4280000
#define HI_CORE2_STACK_SIZE 0x800000 // 8M
#define HI_CORE2_STACK_BASE (HI_CORE3_BASE_ADDR - 16)

#define HI_CORE3_BASE_ADDR (HI_CORE2_BASE_ADDR + HI_CORE2_MEM_SIZE)
#define HI_CORE3_MEM_SIZE 0x4280000
#define HI_CORE3_STACK_SIZE 0x800000 // 8M
#define HI_CORE3_STACK_BASE (HI_SHARED_BASE_ADDR - 16)

#define HI_SHARED_BASE_ADDR (HI_CORE3_BASE_ADDR + HI_CORE3_MEM_SIZE)

#endif /* __HI309X_MEMMAP_H__ */
